1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device capable of changing refresh cycles.
2. Description of the Related Art
A dynamic random access memory (hereinafter, referred to as “DRAM”) is a kind of a semiconductor device that has large capacity and allows 15 random accesses. DRAM stores information in the form of the charge amount stored in its capacitor, and thus, it requires a refresh operation to read and amplify the charge amount before it is lost so as to maintain the original state. The time (referred to as “information holding time” or “retention time”) until the charge amount stored in the capacitor of the memory cell in the DRAM is lost varies depending on memory cells.
The memory cells are distributed continuously from those having short retention time to those having long retention time. The retention time varies primarily because the charge amount of “HIGH data” written into a memory cell is lost due to junction leakage, although it is also affected by surface leakage, or the relation with other neighboring cells. Most memory cells have long retention time. However, a small number of memory cells have short retention time. The cells having such short retention time are saved by replacing them by redundant memory cells. Due to the limited number of redundant circuits, however, some of the memory cells having short retention time may remain unsaved.
The presence of a memory cell having such short retention time causes a defective semiconductor device that does not meet the standards. This leads to degradation of product yields, and an increase of product cost. In order to solve these problems, there is a method of providing a great number of redundant circuits to save all the memory cells having short retention time. If a large number of redundant circuits are provided, however, the chip area of the semiconductor device increases, which would rather increase the product cost.
Techniques to address such a problem are proposed, e.g., in Japanese Patent Laid-Open No. 04-010297 (Patent Document 1) and Japanese Patent Laid-Open No. 08-306184 (Patent Document 2). In a semiconductor device described in Patent Document 1, refresh is carried out more frequently for a specific cell having short retention time than other cells to save the specific cell, to thereby reduce the chip area and decrease the cost. In Patent Document 2, an address of a memory cell having short retention time is stored in a fuse circuit group, to refresh a semiconductor device both in a long period and a short period. For the memory cell to which refresh of the long period is designated, refresh of the short period is skipped, to thereby perform refresh of short period or long period in accordance with the fuse circuit information. According to these documents, short period refresh can be performed on memory cells having short retention time, so as to save them without replacing them by redundant circuits.
Another way of saving memory cells having short data retention time is double refresh. Double refresh, however, requires activation of word lines twice as many as in normal refresh. Thus, it is necessary to double the supply capacity of a power supply circuit provided inside the chip. In cases where the short period refresh is performed with double refresh, the area of the power supply circuit becomes twice that of normal case, which would disadvantageously increase the chip cost.
As described above, the presence of memory cells having short retention time in a semiconductor device problematically causes degradation of the yield. Further, when using double refresh, the power drop inside the chip is large, and the area of the power supply circuit twice that of the normal case is required. This causes the problem of an increased chip cost. Therefore, there is a demand for a double refresh operation suitable for an input manner of the refresh command so as to suppress power supply drop inside the chip.
Further, in contrast to burst refresh in DDR2, in the case of SDRAM prior to DDR1, the number of consecutive refresh commands is determined by the number of refresh cycles described in a data sheet of DRAM, e.g., 8192 times/64 ms or the like. This means that it is possible to hold data of the memory cells if 8192 refresh commands are input every 64 ms. At this time, although the data of the memory cells can be held either with 8192 times/64 ms or with 4096(=8192/2) times/32(=64/2) ms, 8192 times/64 ms cannot achieve the effect of double refresh. This is because the memory cells cannot be refreshed every 32 ms. The effect of double refresh is achieved when the refresh commands are provided at K=2 or greater for 8192=K times/64+K (ms). Accordingly, in the SDRAM prior to DDR1, there may be a case where the effect of double refresh cannot be obtained depending on the input manner of refresh commands by a user. Meanwhile, in the SRAM defined by the standards after DDR2, only eight or less refresh commands can be input consecutively in the manner of burst refresh. Thus, double refresh can be used to obtain the effect of short period refresh.